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| 1/12 february 2003 n 3.6v tolerant inputs and outputs n high speed : t pd = 3.0 ns (max.) at v cc =3.0to3.6v t pd = 3.4 ns (max.) at v cc =2.3to2.7v t pd = 6.8 ns (max.) at v cc =1.8v n power down protection on inputs and outputs n symmetrical output impedance: |i oh |=i ol = 24ma (min) at v cc =3.0v |i oh |=i ol = 18ma (min) at v cc =2.3v |i oh |=i ol =6ma(min)atv cc =1.8v n operating voltage range: v cc (opr) = 1.8v to 3.6v n pin and function compatible with 74 series 16373 n latch-up performance exceeds 300ma (jesd 17) n esd performance: hbm > 2000v (mil std 883 method 3015); mm > 200v description the 74vcx16373 is a low voltage cmos 16 bit d-type latch with 3 state outputs non inverting fabricated with sub-micron silicon gate and five-layer metal wiring c 2 mos technology. it is ideal for low power and very high speed 1.8 to 3.6v applications; it can be interfaced to 3.6v signal environment for both inputs and outputs. these 16 bit d-type latches are bite controlled by two latch enable inputs (nle) and two output enable inputs (oe ). while the nle input is held at a high level, the nq outputs will follow the data input precisely. when the nle is taken low, the nq outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74vcx16373 low voltage cmos 16-bit d-type latch (3-state) with 3.6v tolerant inputs and outputs order codes package tube t & r tssop 74VCX16373TTR tssop pin connection
74vcx16373 2/12 input and output equivalent circuit pin description truth table x : dont care z : high impedance * : q outputs are latched at the time when the le input is taken low logic level. iec logic symbols pin no symbol name and function 1 1oe 3 state output enable input (active low) 2, 3, 5, 6, 8, 9, 11, 12 1q0 to 1q7 3-state outputs 13, 14, 16, 17, 19, 20, 22, 23 2q0 to 2q7 3-state outputs 24 2oe 3 state output enable input (active low) 25 2le latch enable input 36, 35, 33, 32, 30, 29, 27, 26 2d0 to 2d7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1d0 to 1d7 data inputs 48 1le latch enable input 4, 10, 15, 21, 28, 34, 39, 45 gnd ground (0v) 7, 18, 31, 42 v cc positive supply voltage inputs output oe le d q hxx z l l x no change * lhl l lhh h 74vcx16373 3/12 logic diagram this logic diagram has not to be used to estimate propagation delays absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied 1) i o absolute maximum rating must be observed 2) v o 74vcx16373 4/12 dc specifications (2.7v < v cc < 3.6v unless otherwise specified) symbol parameter test condition value unit v cc (v) -40to85c -55to125c min. max. min. max. v ih high level input voltage 2.7to3.6 2.0 2.0 v v il low level input voltage 0.8 0.8 v oh high level output voltage 2.7to3.6 i o =-100 m av cc -0.2 v cc -0.2 v 2.7 i o =-12 ma 2.2 2.2 3.0 i o =-18 ma 2.4 2.4 i o =-24 ma 2.2 2.2 v ol low level output voltage 2.7to3.6 i o =100 m a 0.2 0.2 v 2.7 i o =12 ma 0.4 0.4 3.0 i o =18 ma 0.4 0.4 i o =24 ma 0.55 0.55 i i input leakage current 2.7to3.6 v i = 0 to 3.6v 5 5 m a i off power off leakage current 0 v i or v o = 0 to 3.6v 10 10 m a i oz high impedance output leakage current 2.7to3.6 v i =v ih or v il v o = 0 to 3.6v 10 10 m a i cc quiescent supply current 2.7to3.6 v i =v cc or gnd 20 20 m a v i or v o =v cc to 3.6v 20 20 d i cc i cc incr. per input 2.7to3.6 v ih =v cc -0.6v 750 750 m a 74vcx16373 5/12 dc specifications (2.3v < v cc < 2.7v unless otherwise specified) dc specifications (1.8v < v cc < 2.3v unless otherwise specified) symbol parameter test condition value unit v cc (v) -40to85c -55to125c min. max. min. max. v ih high level input voltage 2.3to2.7 1.6 1.6 v v il low level input voltage 0.7 0.7 v oh high level output voltage 2.3to2.7 i o =-100 m av cc -0.2 v cc -0.2 v 2.3 i o =-6 ma 2.0 2.0 i o =-12 ma 1.8 1.8 i o =-18 ma 1.7 1.7 v ol low level output voltage 2.3to2.7 i o =100 m a 0.2 0.2 v 2.3 i o =12 ma 0.4 0.4 i o =18 ma 0.6 0.6 i i input leakage current 2.3to2.7 v i = 0 to 3.6v 5 5 m a i off power off leakage current 0 v i or v o = 0 to 3.6v 10 10 m a i oz high impedance output leakage current 2.3to2.7 v i =v ih or v il v o = 0 to 3.6v 10 10 m a i cc quiescent supply current 2.3to2.7 v i =v cc or gnd 20 20 m a v i or v o =v cc to 3.6v 20 20 symbol parameter test condition value unit v cc (v) -40to85c -55to125c min. max. min. max. v ih high level input voltage 1.8to2.3 0.7 vcc 0.7 vcc v v il low level input voltage 0.2 vcc 0.2 vcc v v oh high level output voltage 1.8 i o =-100 m av cc -0.2 v cc -0.2 v i o =-6 ma 1.4 1.4 v ol low level output voltage 1.8 i o =100 m a 0.2 0.2 v i o =6 ma 0.3 0.3 i i input leakage current 1.8 v i = 0 to 3.6v 5 5 m a i off power off leakage current 0 v i or v o = 0 to 3.6v 10 10 m a i oz high impedance output leakage current 1.8 v i =v ih or v il v o = 0 to 3.6v 10 10 m a i cc quiescent supply current 1.8 v i =v cc or gnd 20 20 m a v i or v o =v cc to 3.6v 20 20 74vcx16373 6/12 dynamic switching characteristics (t a = 25c, input t r =t f = 2.0ns, c l = 30pf, r l = 500 w) 1) number of outputs defined as "n". measured with "n-1" outputs switching from high to low or low to high. the remaining output is measured in the low state. 2) number of outputs defined as "n". measured with "n-1" outputs switching from high to low or low to high. the remaining output is measured in the high state. 3) parameters guaranteed by design. ac electrical characteristics (c l = 30pf, r l = 500 w, input t r =t f = 2.0ns ) 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low (t oslh =|t plhm -t plhn |, t oshl =|t phlm -t phln |) 2) parameter guaranteed by design symbol parameter test condition value unit v cc (v) t a =25c min. typ. max. v olp dynamic low voltage quiet output (note 1, 3) 1.8 v il =0v v ih =v cc 0.25 v 2.5 0.6 3.3 0.8 v olv dynamic low voltage quiet output (note 1, 3) 1.8 v il =0v v ih =v cc -0.25 v 2.5 -0.6 3.3 -0.8 v ohv dynamic high voltage quiet output (note 2, 3) 1.8 v il =0v v ih =v cc 1.5 v 2.5 1.9 3.3 2.2 symbol parameter test condition value unit v cc (v) -40 to 85 c -55 to 125 c min. max. min. max. t plh t phl propagation delay time dn to qn 1.8 1.5 6.8 1.5 8.0 ns 2.3 to 2.7 1.0 3.4 1.0 4.0 3.0 to 3.6 0.8 3.0 0.8 4.0 t plh t phl propagation delay time le to qn 1.8 1.5 7.8 1.5 9.0 ns 2.3 to 2.7 1.0 3.9 1.0 4.8 3.0 to 3.6 0.8 3.0 0.8 3.9 t pzl t pzh output enable time 1.8 1.5 9.2 1.5 11.0 ns 2.3 to 2.7 1.0 4.6 1.0 6.0 3.0 to 3.6 0.8 3.5 0.8 4.3 t plz t phz output disable time 1.8 1.5 6.8 1.5 7.2 ns 2.3 to 2.7 1.0 3.8 1.0 4.5 3.0 to 3.6 0.8 3.5 0.8 4.1 t s setup time, high or low level dn to le 1.8 2.5 2.5 ns 2.3 to 2.7 1.5 1.5 3.0 to 3.6 1.5 1.5 t h hold time high or low level dn to le 1.8 1.0 1.0 ns 2.3 to 2.7 1.0 1.0 3.0 to 3.6 1.0 1.0 t w le pulse width, high 1.8 4.0 4.0 ns 2.3 to 2.7 1.5 1.5 3.0 to 3.6 1.5 1.5 t oslh t oshl output to output skew time (note1, 2) 1.8 0.75 0.75 ns 2.3 to 2.7 0.5 0.5 3.0 to 3.6 0.5 0.5 74vcx16373 7/12 capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /16 (per circuit) test circuit c l = 30 pf or equivalent (includes jig and probe capacitance) r l =r1=500 w or equivalent r t =z out of pulse generator (typically 50 w ) waveform symbol values symbol parameter test condition value unit v cc (v) t a =25c min. typ. max. c in input capacitance 1.8, 2.5 or 3.3 v in = 0 or v cc 6pf c out output capacitance 1.8, 2.5 or 3.3 v in = 0 or v cc 7pf c pd power dissipation capacitance (note 1) 1.8, 2.5 or 3.3 f in = 10mhz v in = 0 or v cc 20 pf test switch t plh ,t phl open t pzl ,t plz (v cc = 3.0 to 3.6v) 6v t pzl ,t plz (v cc = 2.3 to 2.7v or 1.8v) 2v cc t pzh ,t phz gnd symbol v cc 3.0 to3.6v 2.3 to 2.7v 1.8v v ih 2.7v v cc v cc v m 1.5v v cc /2 v cc /2 v x v ol + 0.3v v ol + 0.15v v ol + 0.15v v y v oh - 0.3v v oh - 0.15v v oh - 0.15v 74vcx16373 8/12 waveform 1 : le to qn propagation delays, le minimum pulse width, dn to le setup and hold times (f=1mhz; 50% duty cycle) waveform 2 : output enable and disable time (f=1mhz; 50% duty cycle) 74vcx16373 9/12 waveform 3 : propagation delay time (f=1mhz; 50% duty cycle) 74vcx16373 10/12 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 d 12.4 12.6 0.488 0.496 e 8.1 bsc 0.318 bsc e1 6.0 6.2 0.236 0.244 e 0.5 bsc 0.0197 bsc k0? 8?0? 8? l 0.50 0.75 0.020 0.030 tssop48 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7065588c 74vcx16373 11/12 dim. mm. inch min. typ max. min. typ. max. a 330 12.992 c 12.8 13.2 0.504 0.519 d 20.2 0.795 n 60 2.362 t 30.4 1.197 ao 8.7 8.9 0.343 0.350 bo 13.1 13.3 0.516 0.524 ko 1.5 1.7 0.059 0.067 po 3.9 4.1 0.153 0.161 p 11.9 12.1 0.468 0.476 tape & reel tssop48 mechanical data 74vcx16373 12/12 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com |
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